The present disclosure relates generally to the field of integrated circuit fabrication and, more particularly, to planarizing topographic features formed on a substrate for integrated circuit technologies.
The demand for storage devices that have a small package size and a high storage density have increased due to the creation of many new applications that require high density storage devices. Accordingly, semiconductor device geometries continue to dramatically decrease in size, to the extent that existing devices routinely have feature geometries smaller than 90 nm. However, such scaling has been plagued by interconnect defects and the increasing complexity of controlling dimensions.
One semiconductor device frequently employed for portable storage is based upon flash memory technology. A generally adopted elemental structure for a flash memory device is the split gate field effect transistor (SGFET) device, which includes a channel region and opposing source/drain regions formed in a semiconductor substrate. A split gate FET also includes a split gate structure typically including a floating gate and a control gate.
The manufacture of such SGFET devices for use in a flash memory device or other semiconductor device requires critical control of device dimensions and material defects which could attribute to device failure. To that end, plasma and/or chemical etch back has proven to provide reasonably accurate control of device dimensions, particularly layer thickness and feature height.
For example, a typical SGFET may incorporate a word line or other interconnect adjacent to the SGFET structure. Such an arrangement may provide more efficient utilization of substrate area, thereby increasing flash device packing density. Plasma and/or chemical etch back is one planarizing process generally employed in the manufacture of the SGFET and adjacent word lines or interconnects to control their shape and geometry. However, existing manufacturing processes, particularly etch back processes, often provide features having poorly-defined profiles. For example, the corners of the surfaces resulting from planarizing by plasma and/or chemical etch back may be rounded. Moreover, planarizing adjacent features of different heights (or “topographic features”) may result in a build-up of excess material in gaps between features of similar height. Such a build-up may result in a jagged edge along a vertical surface of taller topographic features, such that this result is often referred to as a “fence” edge due to the resemblance of the profile to a picket fence. These poorly defined profiles may provide inadequate isolation between features, such as between bit lines, word lines and other interconnects. Consequently, the poorly defined profile and undesired build-up of residue resulting from existing etch back processes can cause electrical shorts between interconnects, thereby limiting device performance and yield, and possibly resulting in catastrophic failure of a device during testing or at the end-user.
Therefore, a method of planarizing topographic features is needed to address the problems discussed above.